anton golovskoi
FPGA Developer
I'm FPGA developer with almost 20 years of experience. I've worked with lots of Xilinx and Intel (Altera) FPGAs including SoCs. I took part in many successful projects mainly concerning digital communication. Since 2012 I have been leading a group of FPGA developers.
I mostly use VHDL during development, but also have an experience with Verilog and System Verilog. I am familiar with MATLAB and Visual Studio. I have implemented lots of complicated algorithms in FPGA including matrix operations and systems with MIMO, certain Wi-Fi and LTE algorithms, various converters, filters, equalizers. I have experience with many hardware interfaces like SPI, I2C, RS-232, PCI-Express, AXI, custom interfaces etc.
I mostly use VHDL during development, but also have an experience with Verilog and System Verilog. I am familiar with MATLAB and Visual Studio. I have implemented lots of complicated algorithms in FPGA including matrix operations and systems with MIMO, certain Wi-Fi and LTE algorithms, various converters, filters, equalizers. I have experience with many hardware interfaces like SPI, I2C, RS-232, PCI-Express, AXI, custom interfaces etc.
Usual FPGA project's workflow
I’m used to work in team together with professionals when everyone does its job: theorists develop algorithms, programmers write high-level code, circuit designers develop circuits. Although I can read C code and look at circuit designs, my main area of responsibility is everything directly related to the development of RTL for the FPGA.
My key principles in work
- Systematic Thinking
I always try to understand, how everything should work in general, all together, not just implement separate modules. It helps to anticipate bottlenecks in advance and take steps to minimize problems.
- Learning NewAs Lewis Carroll wrote: "It takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!"
- Reliability of OperationI focus on reliability of RTL in hardware when I write code. For this purpose I register operations when it is possible; when the operation is really complicated like big mux/demux, it can be split into several registered steps. Synchronous implementation in most cases is easier to debug and more reliable. I try to test everything at first separately, then together. I try to make RTL work as close to the model as possible (preferably bit-by-bit). I make accurate clock domain crossing. I take into account many other important nuances.
Features
Hardware Experience
Intel (Altera) FPGAs: Cyclone IV, Cyclone V, Arria V, Stratix V
During last 5 years I've been working with Xilinx FPGA only: Spartan-6, Kintex-7, Virtex-7, Kintex Ultrascale+, Zynq-7000 and others
Software Experience
Intel (Altera) Quartus II
Xilinx ISE, Vivado
Mentor ModelSim, QuestaSim
MATLAB
Microsoft Visual Studio
GIT
Education
Diploma of Specialist in Radiophysics and Electronics (5-year course), Voronezh State University, Russia
Advanced Training Courses:
- «Development of hardware-software communication systems with NIOS II», Saint-Petersburg, Russia
- «Digital Design with Cadence Encounter», Voronezh, Russia
- «SystemVerilog Design & Verification, SystemVerilog Assertions, Introduction to UVM», Munich, Germany
Languages
Russian – fluent
English – advanced
Spanish – with dictionary
Get in touch
Although I am not always available due to high workload, I'm always looking forward to new opportunities, collaborations and interesting projects, so contact me if you got any. Certain things can be done remotely, let’s discuss it. Also feel free to ask me on any FPGA related topic, I’ll try to give you an answer or directions on where to look for it.
In case of a very interesting offer, I may be interested in relocation.
In case of a very interesting offer, I may be interested in relocation.
a.golovskoy@gmail.com
